// 实验一：基本逻辑门测试激励文件
`timescale 1ns / 1ps

module test_basic_gates;
    // 测试信号声明
    reg a, b;
    wire and_out, or_out, not_out, nand_out, nor_out, xor_out;
    
    // 实例化所有逻辑门模块
    and_gate u_and(.a(a), .b(b), .y(and_out));
    or_gate u_or(.a(a), .b(b), .y(or_out));
    not_gate u_not(.a(a), .y(not_out));
    nand_gate u_nand(.a(a), .b(b), .y(nand_out));
    nor_gate u_nor(.a(a), .b(b), .y(nor_out));
    xor_gate u_xor(.a(a), .b(b), .y(xor_out));
    
    // 监控所有信号
    initial begin
        $monitor("Time=%0t: a=%b, b=%b | AND=%b, OR=%b, NOT(a)=%b, NAND=%b, NOR=%b, XOR=%b", 
                 $time, a, b, and_out, or_out, not_out, nand_out, nor_out, xor_out);
    end
    
    // 生成测试激励
    initial begin
        // 初始化信号
        a = 0;
        b = 0;
        #10;
        
        // 测试所有可能的输入组合
        a = 0; b = 0; #10;
        a = 0; b = 1; #10;
        a = 1; b = 0; #10;
        a = 1; b = 1; #10;
        
        // 结束仿真
        $finish;
    end
    
    // 生成波形文件（可选，用于仿真器查看）
    initial begin
        $dumpfile("basic_gates.vcd");
        $dumpvars(0, test_basic_gates);
    end
endmodule